-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 10.0 Build 218 06/27/2010 SJ Web Edition"

-- DATE "07/18/2012 01:13:21"

-- 
-- Device: Altera EP4CE115F29C7 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	Adder_8bits IS
    PORT (
	LEDR : OUT std_logic_vector(7 DOWNTO 0);
	LEDG : OUT std_logic_vector(1 DOWNTO 0);
	SW : IN std_logic_vector(15 DOWNTO 0)
	);
END Adder_8bits;

-- Design Ports Information
-- LEDR[0]	=>  Location: PIN_G19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[1]	=>  Location: PIN_F19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[2]	=>  Location: PIN_E19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[3]	=>  Location: PIN_F21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[4]	=>  Location: PIN_F18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[5]	=>  Location: PIN_E18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[6]	=>  Location: PIN_J19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDR[7]	=>  Location: PIN_H19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDG[0]	=>  Location: PIN_E21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LEDG[1]	=>  Location: PIN_E22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[0]	=>  Location: PIN_AB28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[8]	=>  Location: PIN_AC25,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[9]	=>  Location: PIN_AB25,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[1]	=>  Location: PIN_AC28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[10]	=>  Location: PIN_AC24,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[2]	=>  Location: PIN_AC27,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[11]	=>  Location: PIN_AB24,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[3]	=>  Location: PIN_AD27,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[12]	=>  Location: PIN_AB23,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[4]	=>  Location: PIN_AB27,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[13]	=>  Location: PIN_AA24,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[5]	=>  Location: PIN_AC26,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[14]	=>  Location: PIN_AA23,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[6]	=>  Location: PIN_AD26,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[15]	=>  Location: PIN_AA22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- SW[7]	=>  Location: PIN_AB26,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF Adder_8bits IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_LEDR : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_LEDG : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_SW : std_logic_vector(15 DOWNTO 0);
SIGNAL \SW[8]~input_o\ : std_logic;
SIGNAL \SW[0]~input_o\ : std_logic;
SIGNAL \B1|WideOr0~0_combout\ : std_logic;
SIGNAL \SW[9]~input_o\ : std_logic;
SIGNAL \B1|W6~combout\ : std_logic;
SIGNAL \SW[1]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~1_cout\ : std_logic;
SIGNAL \B2|WideOr0~2_combout\ : std_logic;
SIGNAL \SW[2]~input_o\ : std_logic;
SIGNAL \SW[10]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~3\ : std_logic;
SIGNAL \B2|WideOr0~4_combout\ : std_logic;
SIGNAL \SW[3]~input_o\ : std_logic;
SIGNAL \SW[11]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~5\ : std_logic;
SIGNAL \B2|WideOr0~6_combout\ : std_logic;
SIGNAL \SW[12]~input_o\ : std_logic;
SIGNAL \SW[4]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~7\ : std_logic;
SIGNAL \B2|WideOr0~8_combout\ : std_logic;
SIGNAL \SW[5]~input_o\ : std_logic;
SIGNAL \SW[13]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~9\ : std_logic;
SIGNAL \B2|WideOr0~10_combout\ : std_logic;
SIGNAL \SW[6]~input_o\ : std_logic;
SIGNAL \SW[14]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~11\ : std_logic;
SIGNAL \B2|WideOr0~12_combout\ : std_logic;
SIGNAL \SW[7]~input_o\ : std_logic;
SIGNAL \SW[15]~input_o\ : std_logic;
SIGNAL \B2|WideOr0~13\ : std_logic;
SIGNAL \B2|WideOr0~14_combout\ : std_logic;
SIGNAL \B2|WideOr0~15\ : std_logic;
SIGNAL \B2|WideOr0~16_combout\ : std_logic;

BEGIN

LEDR <= ww_LEDR;
LEDG <= ww_LEDG;
ww_SW <= SW;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X69_Y73_N16
\LEDR[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B1|WideOr0~0_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(0));

-- Location: IOOBUF_X94_Y73_N2
\LEDR[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~2_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(1));

-- Location: IOOBUF_X94_Y73_N9
\LEDR[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~4_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(2));

-- Location: IOOBUF_X107_Y73_N16
\LEDR[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~6_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(3));

-- Location: IOOBUF_X87_Y73_N16
\LEDR[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~8_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(4));

-- Location: IOOBUF_X87_Y73_N9
\LEDR[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~10_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(5));

-- Location: IOOBUF_X72_Y73_N9
\LEDR[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~12_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(6));

-- Location: IOOBUF_X72_Y73_N2
\LEDR[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~14_combout\,
	devoe => ww_devoe,
	o => ww_LEDR(7));

-- Location: IOOBUF_X107_Y73_N9
\LEDG[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \B2|WideOr0~16_combout\,
	devoe => ww_devoe,
	o => ww_LEDG(0));

-- Location: IOOBUF_X111_Y73_N9
\LEDG[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => ww_LEDG(1));

-- Location: IOIBUF_X115_Y4_N22
\SW[8]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(8),
	o => \SW[8]~input_o\);

-- Location: IOIBUF_X115_Y17_N1
\SW[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(0),
	o => \SW[0]~input_o\);

-- Location: LCCOMB_X114_Y15_N8
\B1|WideOr0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \B1|WideOr0~0_combout\ = \SW[8]~input_o\ $ (\SW[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \SW[8]~input_o\,
	datad => \SW[0]~input_o\,
	combout => \B1|WideOr0~0_combout\);

-- Location: IOIBUF_X115_Y16_N8
\SW[9]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(9),
	o => \SW[9]~input_o\);

-- Location: LCCOMB_X114_Y15_N10
\B1|W6\ : cycloneive_lcell_comb
-- Equation(s):
-- \B1|W6~combout\ = (\SW[8]~input_o\ & \SW[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \SW[8]~input_o\,
	datad => \SW[0]~input_o\,
	combout => \B1|W6~combout\);

-- Location: IOIBUF_X115_Y14_N1
\SW[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(1),
	o => \SW[1]~input_o\);

-- Location: LCCOMB_X114_Y15_N12
\B2|WideOr0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~1_cout\ = CARRY(\SW[1]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \SW[1]~input_o\,
	datad => VCC,
	cout => \B2|WideOr0~1_cout\);

-- Location: LCCOMB_X114_Y15_N14
\B2|WideOr0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~2_combout\ = (\SW[9]~input_o\ & ((\B1|W6~combout\ & (\B2|WideOr0~1_cout\ & VCC)) # (!\B1|W6~combout\ & (!\B2|WideOr0~1_cout\)))) # (!\SW[9]~input_o\ & ((\B1|W6~combout\ & (!\B2|WideOr0~1_cout\)) # (!\B1|W6~combout\ & ((\B2|WideOr0~1_cout\) # 
-- (GND)))))
-- \B2|WideOr0~3\ = CARRY((\SW[9]~input_o\ & (!\B1|W6~combout\ & !\B2|WideOr0~1_cout\)) # (!\SW[9]~input_o\ & ((!\B2|WideOr0~1_cout\) # (!\B1|W6~combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000010111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[9]~input_o\,
	datab => \B1|W6~combout\,
	datad => VCC,
	cin => \B2|WideOr0~1_cout\,
	combout => \B2|WideOr0~2_combout\,
	cout => \B2|WideOr0~3\);

-- Location: IOIBUF_X115_Y15_N8
\SW[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(2),
	o => \SW[2]~input_o\);

-- Location: IOIBUF_X115_Y4_N15
\SW[10]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(10),
	o => \SW[10]~input_o\);

-- Location: LCCOMB_X114_Y15_N16
\B2|WideOr0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~4_combout\ = ((\SW[2]~input_o\ $ (\SW[10]~input_o\ $ (!\B2|WideOr0~3\)))) # (GND)
-- \B2|WideOr0~5\ = CARRY((\SW[2]~input_o\ & ((\SW[10]~input_o\) # (!\B2|WideOr0~3\))) # (!\SW[2]~input_o\ & (\SW[10]~input_o\ & !\B2|WideOr0~3\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110001110",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[2]~input_o\,
	datab => \SW[10]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~3\,
	combout => \B2|WideOr0~4_combout\,
	cout => \B2|WideOr0~5\);

-- Location: IOIBUF_X115_Y13_N8
\SW[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(3),
	o => \SW[3]~input_o\);

-- Location: IOIBUF_X115_Y5_N15
\SW[11]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(11),
	o => \SW[11]~input_o\);

-- Location: LCCOMB_X114_Y15_N18
\B2|WideOr0~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~6_combout\ = (\SW[3]~input_o\ & ((\SW[11]~input_o\ & (\B2|WideOr0~5\ & VCC)) # (!\SW[11]~input_o\ & (!\B2|WideOr0~5\)))) # (!\SW[3]~input_o\ & ((\SW[11]~input_o\ & (!\B2|WideOr0~5\)) # (!\SW[11]~input_o\ & ((\B2|WideOr0~5\) # (GND)))))
-- \B2|WideOr0~7\ = CARRY((\SW[3]~input_o\ & (!\SW[11]~input_o\ & !\B2|WideOr0~5\)) # (!\SW[3]~input_o\ & ((!\B2|WideOr0~5\) # (!\SW[11]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000010111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[3]~input_o\,
	datab => \SW[11]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~5\,
	combout => \B2|WideOr0~6_combout\,
	cout => \B2|WideOr0~7\);

-- Location: IOIBUF_X115_Y7_N15
\SW[12]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(12),
	o => \SW[12]~input_o\);

-- Location: IOIBUF_X115_Y18_N8
\SW[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(4),
	o => \SW[4]~input_o\);

-- Location: LCCOMB_X114_Y15_N20
\B2|WideOr0~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~8_combout\ = ((\SW[12]~input_o\ $ (\SW[4]~input_o\ $ (!\B2|WideOr0~7\)))) # (GND)
-- \B2|WideOr0~9\ = CARRY((\SW[12]~input_o\ & ((\SW[4]~input_o\) # (!\B2|WideOr0~7\))) # (!\SW[12]~input_o\ & (\SW[4]~input_o\ & !\B2|WideOr0~7\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110001110",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[12]~input_o\,
	datab => \SW[4]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~7\,
	combout => \B2|WideOr0~8_combout\,
	cout => \B2|WideOr0~9\);

-- Location: IOIBUF_X115_Y11_N8
\SW[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(5),
	o => \SW[5]~input_o\);

-- Location: IOIBUF_X115_Y9_N22
\SW[13]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(13),
	o => \SW[13]~input_o\);

-- Location: LCCOMB_X114_Y15_N22
\B2|WideOr0~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~10_combout\ = (\SW[5]~input_o\ & ((\SW[13]~input_o\ & (\B2|WideOr0~9\ & VCC)) # (!\SW[13]~input_o\ & (!\B2|WideOr0~9\)))) # (!\SW[5]~input_o\ & ((\SW[13]~input_o\ & (!\B2|WideOr0~9\)) # (!\SW[13]~input_o\ & ((\B2|WideOr0~9\) # (GND)))))
-- \B2|WideOr0~11\ = CARRY((\SW[5]~input_o\ & (!\SW[13]~input_o\ & !\B2|WideOr0~9\)) # (!\SW[5]~input_o\ & ((!\B2|WideOr0~9\) # (!\SW[13]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000010111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[5]~input_o\,
	datab => \SW[13]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~9\,
	combout => \B2|WideOr0~10_combout\,
	cout => \B2|WideOr0~11\);

-- Location: IOIBUF_X115_Y10_N1
\SW[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(6),
	o => \SW[6]~input_o\);

-- Location: IOIBUF_X115_Y10_N8
\SW[14]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(14),
	o => \SW[14]~input_o\);

-- Location: LCCOMB_X114_Y15_N24
\B2|WideOr0~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~12_combout\ = ((\SW[6]~input_o\ $ (\SW[14]~input_o\ $ (!\B2|WideOr0~11\)))) # (GND)
-- \B2|WideOr0~13\ = CARRY((\SW[6]~input_o\ & ((\SW[14]~input_o\) # (!\B2|WideOr0~11\))) # (!\SW[6]~input_o\ & (\SW[14]~input_o\ & !\B2|WideOr0~11\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110001110",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[6]~input_o\,
	datab => \SW[14]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~11\,
	combout => \B2|WideOr0~12_combout\,
	cout => \B2|WideOr0~13\);

-- Location: IOIBUF_X115_Y15_N1
\SW[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(7),
	o => \SW[7]~input_o\);

-- Location: IOIBUF_X115_Y6_N15
\SW[15]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_SW(15),
	o => \SW[15]~input_o\);

-- Location: LCCOMB_X114_Y15_N26
\B2|WideOr0~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~14_combout\ = (\SW[7]~input_o\ & ((\SW[15]~input_o\ & (\B2|WideOr0~13\ & VCC)) # (!\SW[15]~input_o\ & (!\B2|WideOr0~13\)))) # (!\SW[7]~input_o\ & ((\SW[15]~input_o\ & (!\B2|WideOr0~13\)) # (!\SW[15]~input_o\ & ((\B2|WideOr0~13\) # (GND)))))
-- \B2|WideOr0~15\ = CARRY((\SW[7]~input_o\ & (!\SW[15]~input_o\ & !\B2|WideOr0~13\)) # (!\SW[7]~input_o\ & ((!\B2|WideOr0~13\) # (!\SW[15]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000010111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \SW[7]~input_o\,
	datab => \SW[15]~input_o\,
	datad => VCC,
	cin => \B2|WideOr0~13\,
	combout => \B2|WideOr0~14_combout\,
	cout => \B2|WideOr0~15\);

-- Location: LCCOMB_X114_Y15_N28
\B2|WideOr0~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \B2|WideOr0~16_combout\ = !\B2|WideOr0~15\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	cin => \B2|WideOr0~15\,
	combout => \B2|WideOr0~16_combout\);
END structure;


